Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) and programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure.
Advanced FPGAs can include other types of logic blocks in the array in addition to the CLBs and IOBs. For example, the Xilinx Virtex-II Pro™ FPGA includes blocks of Random Access Memory (RAM), blocks implementing multiplier functions, and embedded processor blocks. (The Xilinx Virtex-II Pro FPGA is described in detail in pages 19-71 of the “Virtex-II Pro Platform FPGA Handbook”, published Oct. 14, 2002 and available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which pages are incorporated herein by reference.)
The interconnect structure, CLBs, IOBs, and other logic blocks (e.g., RAM blocks) are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the logic blocks and interconnect are configured. The configuration data can be read from memory (e.g., an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
In many PLDs, the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell. Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as ASIC devices (Application Specific Integrated Circuits). PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology.
The programmable RAM blocks included in some PLDs serve many purposes. For example, programmable RAM blocks can be used as FIFOs (first-in, first-out data storage circuits) to improve data communications between the PLD and other integrated circuits or systems. As another example, data can be stored in the programmable RAM blocks as part of the PLD configuration process, then accessed as necessary to provide (for example) execution instructions for an embedded processor.
RAM blocks in PLDs can take advantage of the programmable nature of the devices to offer more flexibility to system designers. For example, some PLD RAM blocks are configurable with regard to length and width. The Virtex-II Pro Block SelectRAM+ memory block, for example, can be programmed in various depth and width configurations varying from 16K words by 1 bit to 512 words by 36 bits. The Virtex-II Pro Block SelectRAM+ memory block is described, for example, in pages 58-61 of the “Virtex-II Pro Platform FPGA Handbook”, referenced above.
A common method of implementing error correction in a non-configurable RAM is to add an “error correcting code” (ECC) to each word in the RAM array. The ECC provides an encoded version of the entire memory word stored at the same address in the memory, where the memory word includes both the user data and the ECC data. During each write operation to the block RAM, the encoded ECC is generated and stored along with the RAM data. The ECC can include, for example, a Hamming code representation of the memory word. When a Hamming code is used, an ECC of log 2(N)+1 bits (rounded up to the nearest integer) can detect a single error in a memory word of N bits, and report the location of the erroneous bit. The same ECC can also detect the presence of two errors in a memory word of N bits, but cannot report the location of the errors.
During a read operation at the same address, the ECC is recomputed based on the data read from the memory (the read data). The recomputed ECC and the read data are used to determine whether or not an error has occurred in the read data, and also which bit of the read data is in error. Making use of the fact that each bit has only two possible states, the data is corrected by simply flipping the bit that has been identified as the erroneous bit. All of these techniques are well-known in the art of RAM design.
FIG. 1 is a simple block diagram of a well-known non-configurable RAM having error correction capability based on a Hamming code. Each row of N memory cells (each memory word) includes one user data word of M bits plus (log 2(N)+1) ECC bits. In the illustrated RAM, each memory word is 13 bits wide (N=13), each user data word is 8 bits wide (M=8), and the ECC data includes 5 bits (log 2(13)+1=5). While N and M can be much larger numbers, values of 13 and 8 are used in this example, for clarity.
When PLD memory cells are subjected to unusual conditions such as cosmic rays or bombardment by neutrons or alpha particles, a static memory cell can change state. For example, a stored high value can be inadvertently changed to a low value, and vice versa. These “single event upsets” can corrupt the contents of a PLD block RAM. If error correction were available in configurable PLD block RAM, the effects of these single event upsets could be detected and optionally repaired. Therefore, it is clearly desirable to provide error correction in the configurable RAM blocks of PLDs.